Static semiconductor memories are often referred to as SRAMs (static random access memories) because unlike DRAMs, or dynamic random access memories, they do not require periodic refresh signals to restore their stored data.
The bit state in an SRAM is stored in a pair of cross-coupled inverters which form a circuit termed a "flip-flop." The voltage on each of the two outputs of a flip-flop is stable at only one of two possible voltage levels because the operation of the circuit forces one output to a high potential and the other to a low potential. Flip-flops maintain a given state for as long as the circuit receives power, but they can be made to undergo a change in state (i.e., to flip) upon the application of a trigger voltage of sufficient magnitude and duration to the appropriate input.
FIG. 1 is a circuit diagram indicating a typical SRAM cell. The operation of the SRAM cell depicted in FIG. 1 essentially involves two inverters and behaves as a flip-flop. Transistors having gates 19 and 21 serve as access transistors. For example, when transistor 19 is turned on, a logic 1 appearing at node 17 is transmitted to node 16. Node 16 is connected to the gate of pull down transistor 23. Pull-down transistor 23 begins to conduct, causing a logic low to appear at node 13. The low condition at node 13 turns off pull down transistor 28. Consequently, a logic 1 is observed at node 16 through thin film transistor 27. Thus, interlocked transistors 23 and 28 serve as a latch circuit. Once a logic low (0) or logic high (1) is entered at node 16 or node 13, it remains dynamically amplified by the circuit.
Nodes 13 and 16 which serve to couple access transistor, load transistor, and pull down transistors are particularly important in the fabrication of SRAM cells.
Some designers form nodes 13 and/or 16 in a manner schematically partially depicted in FIG. 8 or FIG. 9. For example, in FIG. 8, reference numeral 25.1 denotes an access transistor gate, while reference numeral 23.1 denotes a pull down transistor gate. Gates 25.1 and 23.1 define a current path through junction 13.1. Window 100.1 is created above the current path through junction 13.1, and is subsequently filled with conductive material which links junction 13.1 to a load.
However, the etching process which opens window 100.1 may inadvertently damage underlying junction 13.1 (which may be silicided). Should the junction (or overlying silicide) be damaged, the resistance of the current path defined by gates 25.1 and 23.1 will be increased and overall cell performance will be degraded.
Another approach for forming a node is shown in FIG. 9. Again, access transistor 25.2 and pull down transistor 23.2 define a current path through L-shaped junction 13.2. Window 100.2 is created in the comer of L-shaped junction 13.2. However, the design of FIG. 9 suffers from the same deficiency as that of FIG. 8, namely, that the window is located above the current path defined by the gates. In other words, in the partially completed structures of FIGS. 8 and 9, current is expected to flow beneath (and upwards through) the window. Should the window etching process somewhat adversely affect the underlying silicide or junction, resistance of the defined current path between the gates is undesirably increased.